The present invention relates to a transmission gate circuit in a semiconductor integrated circuit and, more particularly, to a transmission gate circuit having a function of compensating variations in resistance value by a body effect.
Electronic devices such as a computer and controller incorporate a plurality of circuit boards, which are connected to a common bus line. In this case, each circuit board comprises a transmission gate circuit and is connected to the common bus line via the transmission gate circuit. Each circuit board exchanges signals with the bus line via the transmission gate circuit to transmit/receive signals between circuit boards.
FIG. 21 shows the arrangement of transmission gate circuits 2 and 3 associated with the present invention, that are connected to a bus line BL. The transmission gate circuits 2 and 3 are respectively connected to circuit boards which transmit/receive signals via the transmission gate circuits 2 and 3 and bus line BL.
The back gate of an NMOS transistor is biased to the ground potential, unless otherwise specified.
Both the transmission gate circuits 2 and 3 have a CMOS structure and operate as complementary switches. Thus, the ON resistance can be decreased over the voltage range in use from the ground voltage Vss to the power supply voltage Vcc. The transmission gate circuit 3 is an analog switch having the most basic structure. This analog switch comprises n- and p-channel MOS transistors HN1 and HP1. The analog switch has one terminal connected to an input terminal IN2, and the other terminal connected to an output terminal OUT2. The gate of the transistor HN1 receives a signal generated by inputting an enable signal /EN2 to inverters INV4 and INV3, and the gate of the transistor HP1 receives a signal output from the inverter INV4. Since the input and output terminals IN2 and OUT2 function as input/output terminals, they are used not only when a signal is transferred from a circuit (not shown) to the bus line BL but also when a signal is transferred from the bus line BL to the circuit (not shown). The back gate of the transistor HN1 is grounded, whereas the back gate of the transistor HP1 is connected to the power supply voltage Vcc terminal. When the enable signal /EN2 is at high level, the transmission gate circuit 3 is turned into a conductive state to electrically connect the input and output terminals IN2 and OUT2; when the signal /EN2 is at low level, it changes to a non-conductive state.
The transmission gate circuit 2 comprises a switch SW for switching (between the power supply voltage vcc terminal or ground terminal) and a power supply terminal 10, and is turned on when the power supply terminal 10 is connected to the power supply voltage Vcc terminal. At this time, the power supply voltage Vcc is supplied to inverters INV1 and INV2 and the power-supply-side terminal of a transistor P3. When the power supply terminal 10 is connected to the ground terminal, the circuit 2 does not receive any power supply voltage vcc and is turned off.
The transmission gate circuit 2 comprises a body effect compensation circuit in addition to an analog switch which is made up of p- and n-channel MOS transistors P1 and N1 each having one terminal connected to a terminal A connected to an input terminal IN1, and the other terminal connected to a terminal B connected to an output terminal OUT1 connected to the bus line BL. As a body effect compensation circuit for the p-channel MOS transistor P1, the transmission gate circuit 2 comprises a switch made up of p- and n-channel MOS transistors P1P and N1P, a switch made up of p- and n-channel MOS transistors P2P and N2P, and the transistor P3 used for connection to the power supply terminal 10 in the non-conductive state. The switch made up of the transistors P1P and N1P has one terminal connected to the terminal A and the other terminal connected to a back gate Nw of the transistor P1. The switch made up of the transistors P2P and N2P has one terminal connected to the back gate Nw of the transistor P1 and the other terminal connected to the terminal B. The transistor P3 has one terminal connected to the back gate Nw and the other terminal connected to the power supply terminal 10.
As a body effect compensation circuit for the n-channel MOS transistor N1, the transmission gate circuit 2 comprises a switch made up of n- and p-channel MOS transistors N1N and P1N, a switch made up of n- and p-channel MOS transistors N2N and P2N, and an n-channel MOS transistor N2 used for connection to the ground terminal in the non-conductive state. The switch made up of the transistors P1N and N1N has one terminal connected to the terminal A and the other terminal connected to a back gate Pw of the transistor N1. The switch made up of the transistors P2N and N2N has one terminal connected to the back gate Pw of the transistor N1 and the other terminal connected to the terminal B. The transistor N2 has one terminal connected to the back gate Pw of the transistor N1 and the other terminal grounded.
When the power supply voltage Vcc terminal is connected to the power supply terminal 10 by the switch SW and the transmission gate circuit 2 is in the conductive state, the circuit 2 operates as follows. When an enable signal /EN1 is at high level, a signal EN1 inverted by the inverter INV1 is input to the gates of the transistors P1, P1P, P2P, P1N, and P2N to turn them into the conductive state, and the signal /EN1 is input to the gates of the transistors N1, N1P, N2P, N1N, and N2N to turn them conductive. Then, the terminals A and B are electrically connected, and both the transistors P3 and N2 are turned non-conductive.
Since the transistors P1P, N1P, P2P, and N2P are turned conductive, the source and back gate Nw of the transistor P1 are short-circuited to compensate for the body effect on the transistor P1. Since the transistors P1N, N1N, P2N, and N2N are turned conductive, the source and back gate Pw of the transistor N1 are short-circuited to compensate for the body effect on the transistor N1.
When the enable signal /EN1 is at low level, the transistors P1, P1P, P2P, P1N, P2N, N1P, N2P, N1N, N2N, and N1 are turned non-conductive to change the terminals A and B to a non-conductive state. Further, the transistors P3 and N2 are turned conductive so as not to float the back gates Nw and Pw. The back gate Nw is connected to the power supply voltage Vcc terminal by the transistor P3, and the back gate Pw is grounded by the transistor N2.
In the CMOS structure like the transmission gate circuit 2, parasitic diodes by p-n junctions exist at various portions. FIG. 22 shows the sectional structure of a transistor circuit having a CMOS structure formed on a semiconductor substrate 1. This structure is called a triple-well structure. A deep n-well DNW is formed in the surface of the p-type semiconductor substrate 1, a p-well DPW is formed in the n-well DNW, a p-well PW is formed adjacent to the n-well DNW, and an n-well NW is formed in the p-well PW. N-type diffusion layers ND3 and ND4 are formed in the surface of the deep n-well DNW, and biased to the power supply voltage Vcc by the power supply terminal 10 when the circuit 2 is in the ON state. P-type diffusion layers PD13 and PD14 are formed in the surface of the p-well PW and biased to the ground potential.
An NMOS region where an n-channel MOS transistor having n-type diffusion layers ND1 and ND2, a gate oxide GO1, and a gate electrode G1 is formed exists on the surface of the p-well DPW. In this NMOS region, p-type diffusion layers PD1 and PD2 are further formed as terminals of the back gate Pw of the n-channel MOS transistor, and biased to a predetermined voltage level via a terminal Vdpw when the circuit 2 is in the ON state. A PMOS region where a p-channel MOS transistor having p-type diffusion layers PD1 and PD2, a gate oxide G02, and a gate electrode G2 is formed exists on the surface of the n-well NW. In this PMOS region, n-type diffusion layers ND1 and ND2 are further formed as terminals of the back gate Nw of the p-channel MOS transistor, and biased to a predetermined voltage level via a terminal Vnw when the circuit 2 is in the ON state.
This structure allows independent setting of the back-gate potentials of the PMOS and NMOS transistors.
As shown in FIG. 22, parasitic diodes DP exist between the p-type diffusion layers PD11 and PD12 serving as the source and drain of the p-channel MOS transistor, and the n-type diffusion layers ND11 and ND12 formed as terminals of the back gate Nw. In the transmission gate circuit 2 shown in FIG. 21, therefore, the parasitic diodes DP respectively exist between one terminal of the p-channel MOS transistor P1 and the back gate Nw and between one terminal of the p-channel MOS transistor P3 and the back gate Nw.
The presence of the parasitic diodes DP poses the following problems when the transmission gate circuit 2 is in the OFF state, the other transmission gate circuit 3 having the output terminal OUT2 connected to the common bus line BL is in the ON state, and the bus line BL receives a high-level signal.
The transmission gate circuit 2 is in the OFF state, and the switch SW connects the ground terminal to the power supply terminal 10. If the enable signal /EN2 changes to high level, the transmission gate circuit 3 is turned conductive. If a signal of power supply voltage vcc level is input to the input terminal IN2, a signal identical to the power supply voltage Vcc is output onto the bus line BL via the output terminal OUT2.
Let Vf be the built-in potential of the parasitic diode DP present between the drain of the transistor P1 and the back gate Nw. In the transmission gate circuit 2, if the power supply voltage Vcc is higher than the potential vf, the parasitic diode DP is forward-biased. Then, the power supply voltage Vcc on the bus line BL flows a wasteful current to the semiconductor substrate via the output terminal OUT1, the drain and parasitic diode DP of the transistor P1, and the back gate Nw. Moreover, a wasteful current flows to the ground potential via the parasitic diode between the transistor P3 and the grounded terminal 10. Since a signal VGP changes to the ground potential, the PMOS transistor P1 is turned conductive to electrically connect the terminals B and A and flow a current from the terminal B to the terminal A.
This current is generated by the presence of the p-channel MOS transistor in the transmission gate circuit 2. To eliminate this current, the transmission gate circuit 2 may be constituted by only the n-channel MOS transistor N1, and the transistors N1N and N2N may be formed as a body effect compensation circuit for the transistor N1, like a transmission gate circuit 4 shown in FIG. 24.
The transmission gate circuit 4, which transfers a signal by only the n-channel MOS transistor N1, can transfer the ground potential Vss of the terminal A to the bus line BL without any drop. However, it cannot transfer the power supply voltage Vcc without any drop. In other words, the transmission gate circuit 4 can only output to the bus line BL a voltage Vcc-Vthn which has dropped by the threshold voltage Vthn of the transistor N1. As the voltage of a signal to be output comes close to the power supply voltage Vcc, the resistance of the transistor N1 increases to decrease the response speed and cause a signal delay.
In the above description, the problem in the circuit of FIG. 21 arises when the power supply terminal 10 is grounded at the switch SW for switching the power supply terminal 10 between the power supply voltage Vcc terminal and ground terminal.
This problem also arises even with a switch for switching the power supply terminal 10 between the power supply voltage Vcc terminal and open terminal. This will be explained.
In an OFF state in which the power supply terminal 10 is grounded, a steady current may flow from the bus line to the ground potential. In an OFF state in which the power supply terminal 10 is opened, a current for charging the capacitance component present at the open terminal flows from the bus line to the open terminal. This current becomes an extra capacitance load on the bus line when viewed from the circuit 3 which drives the bus line. That is, the current adversely decreases the signal change speed on the bus line.
As described above, in the transmission gate circuits shown in FIGS. 21 to 23, when a plurality of transmission gate circuits are connected to the common bus line, at least one transmission gate circuit is OFF, and another transmission gate circuit outputs a signal higher than the ground voltage Vss to the bus line, a current flows through the parasitic diode of the OFF transmission gate circuit to wastefully consume power.
In addition, a transmission gate circuit, which is constituted without using any p-channel MOS transistor in order to prevent generation of this current, cannot output a signal which swings fully from the ground voltage Vss to the power supply voltage Vcc.